Floating Point Coprocessors

The designer of any microprocessor would like to extend its instruction
set almost infinitely but is limited by the quantity of silicon available (not
to mention the problems of testability and complexity). Consequently, a real
microprocessor represents a compromise between what is desirable and what is
acceptable to the majority of the chip\'s users. For example, the 68020
microprocessor is not optimized for calculations that require a large volume of
scientific (i.e. floating point) calculations. One method to significantly
enhance the performance of such a microprocessor is to add a coprocessor. To
increase the power of a microprocessor, it does not suffice to add a few more
instructions to the instruction set, but it involves adding an auxiliary
processor that works in parallel to the MPU (Micro Processing Unit). A system
involving concurrently operating processors can be very complex, since there
need to be dedicated communication paths between the processors, as well as
software to divide the tasks among them. A practical multiprocessing system
should be as simple as possible and require a minimum overhead in terms of both
hardware and software. There are various techniques of arranging a coprocessor
alongside a microprocessor. One technique is to provide the coprocessor with an
instruction interpreter and program counter. Each instruction fetched from
memory is examined by both the MPU and the coprocessor. If it is a MPU
instruction, the MPU executes it; otherwise the coprocessor executes it. It can
be seen that this solution is feasible, but by no means simple, as it would be
difficult to keep the MPU and coprocessor in step. Another technique is to equip
the microprocessor with a special bus to communicate with the external
coprocessor. Whenever the microprocessor encounters an operation that requires
the intervention of the coprocessor, the special bus provides a dedicated high-
speed communication between the MPU and the coprocessor. Once again, this
solution is not simple. There are more methods of connecting two (or more)
concurrently operating processors, which will be covered in more detail during
the specific discussions of the Intel and Motorola floating point coprocessors.

Motorola Floating Point Coprocessor (FPC) 68882

The designers of the 68000-family coprocessors decided to implement
coprocessors that could work with existing and future generations of
microprocessors with minimal hardware and software overhead. The actual approach
taken by the Motorola engineers was to tightly couple the coprocessor to the
host microprocessor and to treat the coprocessor as a memory-mapped peripheral
lying inside the CPU address space. In effect, the MPU fetches instructions from
memory, and, if an instruction is a coprocessor instruction, the MPU passes it
to the coprocessor by means of the MPU\'s asynchronous data transfer bus. By
adopting this approach, the coprocessor does not have to fetch or interpret
instructions itself. Thus if the coprocessor requires data from memory, the MPU
must fetch it. There are advantages and disadvantages to this design. Most
notably, the coprocessor does not have to deal with, for example, bus errors, as
all fetching is performed by the host MPU. On the other hand, the FPC can not
act as a bus master (making it a non-DMA device), making memory accesses by the
FPC slower than if it were directly connected to the address and data bus.
In order for the coprocessor to work as a memory mapped device, the
designers of the 68000 series of MPU\'s had to set aside certain bit patterns to
represent opcodes for the FPC. In the case of the 68000\'s, the FPC is accessed
through the opcode 1111(2). This number is the same as ‘F\' in hexadecimal
notation, so this bit pattern is often referred to as the F-line.


The 68882 FPC employs an entirely conventional asynchronous bus
interface like all 68000 class devices, and absolutely no new signals whatsoever
are required to connect the unit to an MC 68020 MPU. The 68882 can be configured
to run under a variety of different circumstances, including various sized data
buses and clock speeds. What follows is a diagram of connections necessary to
connect the 68882 to a 68020 or 68030 MPU using a 32-bit data path.

As mentioned previously, all instructions for the FPC are of the F-line
format, that is, they begin with the bit pattern 1111(2). A generic coprocessor
instruction has the following format: the first four bits must be 1111. This
identifies the instruction as being for the coprocessor. The next three bits
identify the coprocessor type, followed by three bits representing the
instruction type. The meaning of the remaining bits varies depending on the
specific instruction.

Coprocessor Operation

When the MPU detects an F-line instruction, it writes the instruction
into the coprocessors memory mapped command